HOT CHIPS 2026 / IBM Z × ARM

One core.
Two architectures.

Explore one core design and two instruction sets — at your own pace, across four interactive stations.

01 — 04

DUAL-ISA
PROCESSOR LAB

Read the engineering story ↗
11high-performance cores
2 nmtechnology node
>5.7 GHzannounced frequency
Z + Armnative support per core

Announced design targets · future IBM Z / LinuxONE · IBM · 24.08.2026 ↗

01 / ARCHITECTURE EXPLORER

Meet the core. Eleven times.

Choose a core to examine its capabilities.

IBM Z × ARMCONCEPT / 2026
ILLUSTRATIVE PLACEMENTNEBU / LAB

Conceptual architecture visualization — not an official IBM die layout.

02 / INSTRUCTION LAB

Different words. Same result.

Press Step to execute the first instruction on both architectures.

· Choose another core

IBM Z

    DATA MEMORY · BYTE ADDRESS 0x80

    Listing PC: ·

    Arm AArch64

      DATA MEMORY · BYTE ADDRESS 0x80

      Listing PC: ·

      What exactly is executed?

      IBM Z: LGHI, AGR, CGR, BRC, STG, LG. Arm A64: MOVZ, ADD (register), CMP (register), B.EQ, STR and LDR (64-bit, base register). Only the forms in these listings are supported. 64-bit integer wrapping, IBM condition codes and Arm CMP flags are modeled. IBM Z data uses big-endian order; the Arm example uses little-endian order. Arm X4 starts at byte address 128.

      The PC is a zero-based source-listing index, not a byte address. Labels resolve to listing indices. Reaching the end stops this teaching harness; no invented HALT instruction is used. There is no OS, privilege, exception, virtual memory or cycle-accurate pipeline model.

      Live execution trace
      

      03 / ONE PROCESSOR, TWO WORLDS
      Keep the conversation close.
      Submit a synthetic transaction to follow its processing.
      

      Synthetic transaction
      Fictional data only. No network calls or banking connection.
      1. Validate · Z application
      2. Request · service interface
      3. Risk rule · Arm service
      4. Response · service interface
      5. Complete · Z application
      REQUEST
      RESPONSE
      Deterministic rule, not a trained AI model: score = min(100, floor(amount / 1000) × 10 + (cross-region ? 25 : 0)). Score ≥ 50 → review. The announced AI block is hardware context; this rule runs in JavaScript. Placement changes the conceptual transport boundary, not the result or a measured execution time.
      

      04 / THE ARCHITECTURAL DIFFERENCE
      Where does the ISA live?
      Choose an architecture to see how its instruction sets are supported.
      Conceptual comparison. No benchmark or claim about a disclosed internal pipeline.
      

      Conceptual teaching model based on IBM’s 2026 announcement — not a real dual-ISA emulator or a released mainframe.
      

      THE ENGINEERING STORY
      An announcement worth understanding.
      What IBM announced, what an ISA promises to software, and what remains unknown.
      IBM Z meets Arm — read the full article ↗
      

      Research sources & model limitations
      Confirmed announcement: 11 cores, 2 nm, more than 5.7 GHz, native support for both ISAs within each core, AI inference acceleration, I/O DPU and a large cache architecture. Future design; no commercial release date established here.
      The chip layout, allocation timeline and service workflow are original teaching models. This is not a full IBM Z or Arm emulator, a z/OS instance, or a benchmark. Telum II powers the existing z17 generation; the 2026 design is separate.
      Independent project by Dennis Hilk. IBM, IBM Z, LinuxONE and Arm are trademarks of their respective owners. No endorsement by IBM or Arm.